M. Arulkumar* and M. Chandrasekaran Pages 1 - 12 ( 12 )
Aim: FIR filter is the most widely used device in DSP applications, which is also applicable to integrate with image processing approaches. The ALU based FIR structure is applicable for various devices to increase the performance. The ALU design operation includes accumulation, subtraction, shifting, multiplication and filtering. Existing methods are designed with various multipliers like Wallace tree multiplier, DADDA multiplier, Vedic multiplier and adders like carry select adder, and carry look-ahead adder.
Objective: The main objective is to reduce the area, delay and power factors since optimum VLSI circuit is employed in this paper. By these adders and multipliers, operations are independently enabling main operations in DSP. The FIR filter is designed using a MAC unit with clock regenerative comparators. Introduction: In the field of VLSI industry, the low power, reduced time, and area-efficient designs are mostly preferred for various applications. Adders and multipliers play a vital role in VLSI circuit designs. The recent electronics industry uses a digital filter for various real-time applications. This utilizes Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters, here the FIR filter is most stable than IIR filter. This FIR filter indicates the impulse signal into finite form and it is used mainly in DSP processors for getting high-speed. In these two ALU and FIR circuits, the adders and multiplier block’s usage is increased it consumes much power.
Method: The proposed research work uses the clock-gating technique for reducing power consumption. Here the latch-based clock gating technique provides an efficient result. XOR-based logic circuit reduces the design complexity and utilizes the less area. Carry save accumulator is a digital adder used for addition. It provides the two set of output, which is partial sum and carry output. The ripple carry adder uses full adder circuit for its operation. It propagates the carry value in last bit. For addition, the combination of CSA and RCA utilizes less area, high speed and provides the better through put. In multiplier block, the booth multiplier algorithm is used with XOR-based logic. Here this proposed FIR filter is designed for performing image filtration of retina image. This process improves the better visualization approach on medical field.
Results: Thus, the design and analysis of proposed ALU based FIR filter with latch-based clock gating technique is designed and analyzed various parameters. Here the modified adders and multiplier is proposed for efficiency of the system. The modified carry save adder is proposed with combining ripple carry adder logic for improving the adders’ performance. The enhanced booth multiplier is designed using add and shift method for reducing the number of stages to calculate the result. This process is applied to perform image processing of retina image. After designing the ALU based FIR filter structure in VLSI environment, the image is loaded on the MATLAB as the .png format then it is converted into hex file, which is read from the Xilinx to perform filtering the process. Then the ‘dataout’ is converted into binary file to obtain the result of filtering process. The enhanced booth multiplier reduces the delay by reducing the number of stages to calculate the result. Here the clock gating technique is proposed with the latch- based design for reducing the dynamic and clock power consumption. The number of adder’s circuit in both ALU and FIR circuits is less since it improves the overall efficiency of the system.
Conclusion: Thus the proposed methodology concluded that design and analysis of ALU based FIR filter for medical image processing gives the efficient result on the way of achieving the factors such that power (Static & Dynamic), Delay (Path delay) area utilization, MSE and PSNR. Here the image processing of FIR results to MSE and PSNR values, which obtained the better result than the existing VLSI based image processing works. The Latch- based clock gating circuit is connected with the proposed circuit, based on the gated clock signal it optimizes the gated circuit of the whole design since it also reduces the error and provides the efficient power report. This proposed VLSI model is simulated using Xilinx ISE 14.5 and Modelsim synthesizes it; here with the help of MATLAB with the adaptation of 2018a tool, the image filtering was done.
FIR filter, ALU design, Retina image, Modified CSA, Enhanced Booth multiplier, Gate level design, Latch based Clock gating technique.
Dept of Electronics and Communication Engineering, Government College of Engineering Bargur, Krishnagiri- 635104,, Dept of Electronics and Communication Engineering, Government College of Engineering Bargur, Krishnagiri- 635104